Release Note for BCM570x BOOT Code Firmware ================================================== Version 2.4: 1. Fixed cable unplug/replug problem (CQ#1998). Version 2.3: 1. Added 100Mbps WOL on A3/B5 boards. 2. Fixed zero mac address when enabling WOL on fiber card (CQ#2236). Version 2.2: 1. Initialize PME Status upon the first time power-up. Version 2.1: 1. Fixed bug on WOL. 2. Temporarily disable BCM5703 support. 3. Fixed link loss on fiber card. Version 2.0: 1. Added WOL support 2. Added BCM5703 support Version 1.9: 1. Added features so that neccessary manufacturing information is stored in the shared memory. This allows host driver can query these information. Version 1.8: 1. Fixed a problem where PXE is not operatable in version 1.7. Version 1.7: 1. Added logic for 1.3v and 1.8v voltage source. 2. Added logic forcing PCI mode. Version 1.6: 1. Added BCM5701 support. * Initialize BCM5701 to use PHY LED mode. * Initialize BCM5701's PHY to advertise 10/100/1000. 2. Timer prescaler is now initialized to reflect 66Mhz core clock. Version 1.5: 1. Added BCM5700 Fiber support. Version 1.4: 1. Initialize BAR after first reset. Version 1.3: 1. Changed so that default manufacturing information now has proper power consumption and dissipation. Version 1.2: 1. Fixed a problem where firmware has problem accessing PHY registers during bootup time for NIC rev.12 and above. Version 1.1: 1. Format of ASIC revision ID has been changed. Changed to generate PCI revision ID correctly. ASIC Rev. PCI Revision ID ======== =============== B0 0x10 B1 0x11 Version 1.0: 1. Initialize PHY LED mode based on subsystem vendor ID. * Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x0) * Other : link/speed mode (MII 0x10 = 0x2) Version 0.8: 1. Initialize PHY LED mode based on subsystem device ID. * Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x2) * Other : link/speed mode (MII 0x10 = 0x0) Version 0.7: 1. Initialize PHY (BCM5401) with scripts so that NIC has link after power-on-reset before driver is loaded. Version 0.6: 1. Initialize Chip Revision ID in PCI configuration space. Version 0.5: 1. Added logic to perform PHY H/W reset. 2. Initialize VPD delay so that BIOS can access VPD. Version 0.4: Initial release.